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<!@TC:0>
<a name=mapperReport1>Synopsys Actel Technology Mapper, Version mapact, Build 729R, Built Jun 20 2012 09:47:40</a>
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP1 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:0> | Running in 64-bit mode. 
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:0> | Gated clock conversion disabled  
@N:<a href="@N:MF547:@XP_HELP">MF547</a> : <!@TM:0> | Generated clock conversion disabled  

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)



Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

@N: : <a href="d:\02.workspace\03.actel\project\gsmpbx\hdl\gsmpbx.v:110:0:110:6:@N::@XP_MSG">gsmpbx.v(110)</a><!@TM:0> | Found counter in view:work.gsmpbx(verilog) inst mc[10:0]

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

@N:<a href="@N:FP130:@XP_HELP">FP130</a> : <!@TM:0> | Promoting Net mclk_c_c on CLKBUF  mclk_pad  

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

Writing Analyst data base D:\02.workspace\03.actel\project\gsmpbx\synthesis\gsmpbx.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

Writing EDIF Netlist and constraint files
F-2012.03M-SP1 

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

Found clock gsmpbx|mclk with period 10.00ns 


<a name=timingReport2>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Thu May 23 22:22:13 2013
#


Top view:               gsmpbx
Library name:           PA3
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        proasic3
Paths requested:        5
Constraint File(s):    D:\02.workspace\03.actel\project\gsmpbx\synthesis\gsmpbx_sdc.sdc
                       
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:0> | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:0> | Clock constraints cover only FF-to-FF paths associated with the clock. 



<a name=performanceSummary3>Performance Summary </a>
*******************


Worst slack in design: -4.110

                   Requested     Estimated     Requested     Estimated                Clock        Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
-------------------------------------------------------------------------------------------------------------------
gsmpbx|mclk        100.0 MHz     54.9 MHz      10.000        18.220        -4.110     declared     default_clkgroup
===================================================================================================================





<a name=clockRelationships4>Clock Relationships</a>
*******************

Clocks                    |    rise  to  rise   |    fall  to  fall    |    rise  to  fall   |    fall  to  rise  
------------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack  |  constraint  slack   |  constraint  slack  |  constraint  slack 
------------------------------------------------------------------------------------------------------------------
gsmpbx|mclk  gsmpbx|mclk  |  10.000      6.444  |  10.000      -1.781  |  No paths    -      |  5.000       -4.110
==================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo5>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport6>Detailed Report for Clock: gsmpbx|mclk</a>
====================================



<a name=startingSlack7>Starting Points with Worst Slack</a>
********************************

             Starting                                      Arrival           
Instance     Reference       Type       Pin     Net        Time        Slack 
             Clock                                                           
-----------------------------------------------------------------------------
mc[8]        gsmpbx|mclk     DFN0E1     Q       mc[8]      0.653       -4.110
mc[6]        gsmpbx|mclk     DFN0E1     Q       mc[6]      0.653       -3.834
mc[9]        gsmpbx|mclk     DFN0E1     Q       mc[9]      0.653       -3.827
mc[7]        gsmpbx|mclk     DFN0E1     Q       mc[7]      0.653       -3.690
mc[10]       gsmpbx|mclk     DFN0E1     Q       mc[10]     0.653       -3.592
mc[0]        gsmpbx|mclk     DFN0E1     Q       mc[0]      0.653       -2.716
mc[5]        gsmpbx|mclk     DFN0E1     Q       mc[5]      0.527       -2.657
mc[2]        gsmpbx|mclk     DFN0E1     Q       mc[2]      0.653       -2.623
mc[1]        gsmpbx|mclk     DFN0E1     Q       mc[1]      0.653       -2.605
mc[4]        gsmpbx|mclk     DFN0E1     Q       mc[4]      0.527       -2.487
=============================================================================


<a name=endingSlack8>Ending Points with Worst Slack</a>
******************************

               Starting                                            Required           
Instance       Reference       Type     Pin     Net                Time         Slack 
               Clock                                                                  
--------------------------------------------------------------------------------------
pcm_fs[0]      gsmpbx|mclk     DFN1     D       pcm_fs_9[0]        4.461        -4.110
pcm_fs[4]      gsmpbx|mclk     DFN1     D       pcm_fs_9[4]        4.461        -4.110
spi_cs[4]      gsmpbx|mclk     DFN1     D       spi_cs_RNO[4]      4.426        -3.834
pcm_fs[3]      gsmpbx|mclk     DFN1     D       pcm_fs_9[3]        4.461        -3.175
pcm_fs[5]      gsmpbx|mclk     DFN1     D       pcm_fs_9[5]        4.461        -3.175
spi_cs[0]      gsmpbx|mclk     DFN1     D       spi_cs6            4.461        -3.151
pcm_sel[7]     gsmpbx|mclk     DFN1     D       pcm_sel_RNO[7]     4.426        -3.081
pcm_sel[2]     gsmpbx|mclk     DFN1     D       pcm_sel_RNO[2]     4.426        -3.069
pcm_sel[6]     gsmpbx|mclk     DFN1     D       pcm_sel_RNO[6]     4.426        -3.069
pcm_sel[0]     gsmpbx|mclk     DFN1     D       pcm_sel_RNO[0]     4.426        -3.061
======================================================================================



<a name=worstPaths9>Worst Path Information</a>
<a href="D:/02.workspace/03.actel/project/gsmpbx/synthesis/synlog/gsmpbx_fpga_mapper.srr:srsfD:\02.workspace\03.actel\project\gsmpbx\synthesis\gsmpbx.srs:fp:9181:10411:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            0.539
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.461

    - Propagation time:                      8.572
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.110

    Number of logic level(s):                4
    Starting point:                          mc[8] / Q
    Ending point:                            pcm_fs[0] / D
    The start point is clocked by            gsmpbx|mclk [falling] on pin CLK
    The end   point is clocked by            gsmpbx|mclk [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
mc[8]               DFN0E1     Q        Out     0.653     0.653       -         
mc[8]               Net        -        -       1.423     -           6         
mc_RNITL64_0[9]     OR2        B        In      -         2.077       -         
mc_RNITL64_0[9]     OR2        Y        Out     0.646     2.723       -         
N_129               Net        -        -       1.526     -           7         
mc_RNITFJF[10]      NOR2A      B        In      -         4.249       -         
mc_RNITFJF[10]      NOR2A      Y        Out     0.407     4.656       -         
N_220               Net        -        -       1.994     -           12        
pcm_fs_RNO_1[0]     NOR3B      B        In      -         6.649       -         
pcm_fs_RNO_1[0]     NOR3B      Y        Out     0.624     7.273       -         
N_188               Net        -        -       0.322     -           1         
pcm_fs_RNO[0]       AO1        C        In      -         7.595       -         
pcm_fs_RNO[0]       AO1        Y        Out     0.655     8.250       -         
pcm_fs_9[0]         Net        -        -       0.322     -           1         
pcm_fs[0]           DFN1       D        In      -         8.572       -         
================================================================================
Total path delay (propagation time + setup) of 9.110 is 3.524(38.7%) logic and 5.586(61.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.000
    - Setup time:                            0.539
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.461

    - Propagation time:                      8.572
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.110

    Number of logic level(s):                4
    Starting point:                          mc[8] / Q
    Ending point:                            pcm_fs[4] / D
    The start point is clocked by            gsmpbx|mclk [falling] on pin CLK
    The end   point is clocked by            gsmpbx|mclk [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
mc[8]               DFN0E1     Q        Out     0.653     0.653       -         
mc[8]               Net        -        -       1.423     -           6         
mc_RNITL64_0[9]     OR2        B        In      -         2.077       -         
mc_RNITL64_0[9]     OR2        Y        Out     0.646     2.723       -         
N_129               Net        -        -       1.526     -           7         
mc_RNITFJF[10]      NOR2A      B        In      -         4.249       -         
mc_RNITFJF[10]      NOR2A      Y        Out     0.407     4.656       -         
N_220               Net        -        -       1.994     -           12        
pcm_fs_RNO_1[4]     NOR3B      B        In      -         6.649       -         
pcm_fs_RNO_1[4]     NOR3B      Y        Out     0.624     7.273       -         
N_196               Net        -        -       0.322     -           1         
pcm_fs_RNO[4]       AO1        C        In      -         7.595       -         
pcm_fs_RNO[4]       AO1        Y        Out     0.655     8.250       -         
pcm_fs_9[4]         Net        -        -       0.322     -           1         
pcm_fs[4]           DFN1       D        In      -         8.572       -         
================================================================================
Total path delay (propagation time + setup) of 9.110 is 3.524(38.7%) logic and 5.586(61.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.000
    - Setup time:                            0.574
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.426

    - Propagation time:                      8.260
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.834

    Number of logic level(s):                4
    Starting point:                          mc[6] / Q
    Ending point:                            spi_cs[4] / D
    The start point is clocked by            gsmpbx|mclk [falling] on pin CLK
    The end   point is clocked by            gsmpbx|mclk [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
mc[6]               DFN0E1     Q        Out     0.653     0.653       -         
mc[6]               Net        -        -       1.526     -           7         
mc_RNI3F99[10]      NOR2       B        In      -         2.179       -         
mc_RNI3F99[10]      NOR2       Y        Out     0.646     2.826       -         
N_216               Net        -        -       1.526     -           7         
mc_RNITFJF[9]       NOR2B      B        In      -         4.352       -         
mc_RNITFJF[9]       NOR2B      Y        Out     0.516     4.868       -         
N_230               Net        -        -       1.639     -           8         
spi_cs_RNO_0[4]     NOR3B      B        In      -         6.507       -         
spi_cs_RNO_0[4]     NOR3B      Y        Out     0.624     7.131       -         
spi_cs_RNO_0[4]     Net        -        -       0.322     -           1         
spi_cs_RNO[4]       AOI1       C        In      -         7.452       -         
spi_cs_RNO[4]       AOI1       Y        Out     0.487     7.939       -         
spi_cs_RNO[4]       Net        -        -       0.322     -           1         
spi_cs[4]           DFN1       D        In      -         8.260       -         
================================================================================
Total path delay (propagation time + setup) of 8.834 is 3.500(39.6%) logic and 5.334(60.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.000
    - Setup time:                            0.539
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.461

    - Propagation time:                      8.288
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.827

    Number of logic level(s):                4
    Starting point:                          mc[9] / Q
    Ending point:                            pcm_fs[0] / D
    The start point is clocked by            gsmpbx|mclk [falling] on pin CLK
    The end   point is clocked by            gsmpbx|mclk [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
mc[9]               DFN0E1     Q        Out     0.653     0.653       -         
mc[9]               Net        -        -       1.279     -           5         
mc_RNITL64_0[9]     OR2        A        In      -         1.933       -         
mc_RNITL64_0[9]     OR2        Y        Out     0.507     2.440       -         
N_129               Net        -        -       1.526     -           7         
mc_RNITFJF[10]      NOR2A      B        In      -         3.966       -         
mc_RNITFJF[10]      NOR2A      Y        Out     0.407     4.373       -         
N_220               Net        -        -       1.994     -           12        
pcm_fs_RNO_1[0]     NOR3B      B        In      -         6.366       -         
pcm_fs_RNO_1[0]     NOR3B      Y        Out     0.624     6.990       -         
N_188               Net        -        -       0.322     -           1         
pcm_fs_RNO[0]       AO1        C        In      -         7.311       -         
pcm_fs_RNO[0]       AO1        Y        Out     0.655     7.967       -         
pcm_fs_9[0]         Net        -        -       0.322     -           1         
pcm_fs[0]           DFN1       D        In      -         8.288       -         
================================================================================
Total path delay (propagation time + setup) of 8.827 is 3.385(38.4%) logic and 5.442(61.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.000
    - Setup time:                            0.539
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.461

    - Propagation time:                      8.288
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.827

    Number of logic level(s):                4
    Starting point:                          mc[9] / Q
    Ending point:                            pcm_fs[4] / D
    The start point is clocked by            gsmpbx|mclk [falling] on pin CLK
    The end   point is clocked by            gsmpbx|mclk [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
mc[9]               DFN0E1     Q        Out     0.653     0.653       -         
mc[9]               Net        -        -       1.279     -           5         
mc_RNITL64_0[9]     OR2        A        In      -         1.933       -         
mc_RNITL64_0[9]     OR2        Y        Out     0.507     2.440       -         
N_129               Net        -        -       1.526     -           7         
mc_RNITFJF[10]      NOR2A      B        In      -         3.966       -         
mc_RNITFJF[10]      NOR2A      Y        Out     0.407     4.373       -         
N_220               Net        -        -       1.994     -           12        
pcm_fs_RNO_1[4]     NOR3B      B        In      -         6.366       -         
pcm_fs_RNO_1[4]     NOR3B      Y        Out     0.624     6.990       -         
N_196               Net        -        -       0.322     -           1         
pcm_fs_RNO[4]       AO1        C        In      -         7.311       -         
pcm_fs_RNO[4]       AO1        Y        Out     0.655     7.967       -         
pcm_fs_9[4]         Net        -        -       0.322     -           1         
pcm_fs[4]           DFN1       D        In      -         8.288       -         
================================================================================
Total path delay (propagation time + setup) of 8.827 is 3.385(38.4%) logic and 5.442(61.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A3P060_VQFP100_STD
<a name=cellreport10>Report for cell gsmpbx.verilog</a>
  Core Cell usage:
              cell count     area count*area
               AO1     5      1.0        5.0
              AO1A     3      1.0        3.0
              AO1D     1      1.0        1.0
              AOI1     6      1.0        6.0
             AOI1B     1      1.0        1.0
              AX1A     1      1.0        1.0
               GND     1      0.0        0.0
              MX2A     2      1.0        2.0
              MX2B     1      1.0        1.0
              NOR2     6      1.0        6.0
             NOR2A     7      1.0        7.0
             NOR2B     3      1.0        3.0
              NOR3     4      1.0        4.0
             NOR3A    11      1.0       11.0
             NOR3B    16      1.0       16.0
             NOR3C    11      1.0       11.0
               OA1     5      1.0        5.0
              OA1A     1      1.0        1.0
              OA1B     3      1.0        3.0
              OA1C     2      1.0        2.0
              OAI1     4      1.0        4.0
               OR2    39      1.0       39.0
              OR2A     6      1.0        6.0
              OR2B    17      1.0       17.0
              OR3A     2      1.0        2.0
              OR3B     1      1.0        1.0
              OR3C     2      1.0        2.0
               VCC     1      0.0        0.0
              XA1B     1      1.0        1.0
              XA1C     4      1.0        4.0


            DFN0E1    11      1.0       11.0
              DFN1    31      1.0       31.0
                   -----          ----------
             TOTAL   209               207.0


  IO Cell usage:
              cell count
            CLKBUF     1
             INBUF    18
            OUTBUF    42
                   -----
             TOTAL    61


Core Cells         : 207 of 1536 (13%)
IO Cells           : 61

  RAM/ROM Usage Summary
Block Rams : 0 of 4 (0%)

Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 38MB peak: 102MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu May 23 22:22:13 2013

###########################################################]

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